Location: Chengdu, Sichuan Province, China
or Santa Clara, California, US

Industry: Semiconductor
Company Name: GLF Integrated Power / Jiefu Microelectronics
Website: www.glfipower.com
Company Size: 60+
Founded: 2013
Phone: 86-28-64109885 or 13980970522
Contact: This email address is being protected from spambots. You need JavaScript enabled to view it. 

About GLF

GLF Integrated Power, Inc. is a Silicon Valley, California Semiconductor Company. Founded in 2013, we provide breakthrough, ultra-efficient, ultra-small, silicon power control and protection IC. We launched our first IQSmartTM, ultra-efficient load-switch device in 2015 and achieved immediate design wins at major wearables, SSD, and portable device manufacturers. Our portfolio is now actively expanding to more efficient power protection analog ICs. JieFu Microelectronics was set up in Chengdu in 2016.

About the Position

  • Title: Design Manager
  • Reports to: Head of R&D
  • Location: Chengdu
  • Relocation: Eligible
  • Seniority Level: Mid-Senior Level
  • Employment Type: Full-time

Job Responsibility

  1. Design chips at transistor level to meet part definition as well as get involved in part definition with system/marketing team on power protection ICs such as front-end power protection ICs and system protection/management ICs
  2. Cooperate with layout engineer for floor plan and work with test/application team to release the part to market
  3. Responsible for leading the overall work of the department, organizing and supervising team members to complete all tasks within the scope of responsibility of the department, and strengthening the cooperation, and cooperation with related departments
  4. Responsible for organizing the formulation of the company's technical management system and technical process standards, and responsible for formulating or modifying technical regulations
  5. Responsible for the archive all technical documents of the department including schematics, drawing, and related software.

Qualification

  1. 8 years + of experience in analog power IC design, with a master's degree or above in EE;
  2. Strong analog design skills and understanding of power semiconductor knowledge;
  3. Rich experience in leading power management related IC design like DC-DC converter, charger, LDO, etc. and releasing to market with volume
  4. Understand the layout of analog power IC;
  5. Familiar with EAD tools of Cadence/Mentor Graphics/Synopsys or other simulation tools;
  6. Possess interpersonal skills and can work in a team environment;
  7. Good interpersonal skills, written communication and expression skills;
  8. Good English written and oral communication skills.

Competitive Benefits

  • Help the candidate to get work permission in China
  • Provide accommodation
  • Provide round-trip air tickets once a year
  • Provide Commercial insurance
  • Enjoy China Holiday benefits
  • Participate Various team activities
  • Compensation negotiable

Please send your CV or Resume to This email address is being protected from spambots. You need JavaScript enabled to view it.

For more contact Info navigate to our Contact Page

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